ADC or Analog to Digital Converter is device which changes analog signals i.e 0 & 1 into digital signals. The ADC is used to convert an analog voltage (a voltage that vary continuously within a known range) to a 10-bit digital value. For instance, it can be used to log the output of a sensor (temperature, pressure, etc) at regular intervals, or to take some action in function of the measured variable value.
WORKING
At the input of the ADC it is an analog multiplexer, which is used to select between eight analog inputs. That means that you can convert up to eight signals (not at the same time of course). At the end of the conversion, the corresponding value is transferred to the registers ADCH and ADCL. As the AVR's registers are 8-bit wide, the 10-bit value can only be held in two registers.
The analog voltage at the input of the ADC must be greater than 0V, and smaller than the ADC's reference voltage AREF. The reference voltage is an external voltage you must supply at the AREF pin of the chip. The value the voltage at the input is converted to can be calculated with the following formula:
ADC conversion value = round( (vin/vref)*1023)
Since it is a 10-bit ADC, you have 1024(1024=2^10) possible output values (from 0 to 1023). So, if vin is equal to 0V, the result of the conversion will be 0, if vin is equal to vref, it will be 1023, and if vin is equal to vref/2 it will be 512. As you can see, since you are converting a continuous variable (with infinite possible values) to a variable with a finite number of possible values (elegantly called a "discrete variable"), the ADC conversion produces an error, known as "quantization error".
Feature of ADC of the AVR
The AVR features inbuilt ADC in almost all its MCU. In ATMEGA16/32, PORTA contains the ADC pins.
Ø 10 bit Resolution
Ø 0.5 LSB Integral Non linearity
Ø ±2 LSB Absolute Accuracy
Ø 13-260 µs Conversion Time
Ø Up to 15 KSPS at Max Resolution
Ø 8 Multiplexed Single Ended Input channels
Ø 7 Different Input channels
Ø 2 Different Input channels with optional Gain of 10X and 200X
Ø 0-Vcc ADC Input Voltage Range
Ø Selectable 2.56 ADC Reference Voltage
Ø Free running or Single conversion Mode
Ø ADC Start conversion by Auto Triggering on Interrupt Sources
Ø Interrupt on ADC Conversion Complete
Ø Sleep Mode Noise canceller
More about ADC:
- ADC Prescaler
- ADC Registers – ADMUX, ADCSRA, ADCH, ADCL and SFIOR
ADC Prescaler
The ADC of the AVR converts analog signal into digital signal at regular interval. This interval is determined by the clock frequency. In general, the ADC operates within a frequency range of 50kHz to 200kHz. But the CPU clock frequency is much higher (in the order of MHz). So to achieve it, frequency division must take place.
ADC Registers
- ADMUX (ADC Multiplexer Selection Register)
- ADCSRA (ADC Control and Status Register A)
- ADCL (ADC Data Registers Low)
- ADCH (ADC Data Registers High)
ADMUX register
This register is used to select which of the 8 channel (between ADC0 to ADC7) will be the input to the ADC. Since there are 8 possible inputs, only the 3 least significant bits of this register are used. The following table describe the setting of ADMUX.
The ADC needs a reference voltage to work upon. For this we have a three pins AREF, AVCC and GND. We can supply our own reference voltage across AREF and GND. For this, choose the first option. Apart from this case, you can either connect a capacitor across AREF pin and ground it to prevent from noise, or you may choose to leave it unconnected. If you want to use the VCC (+5V), choose the second option. Or else, choose the last option for internal Vref.
|
MUX2 |
MUX1 |
MUX0 |
SELECTED INPUT |
|
0 |
0 |
0 |
ADC0 |
|
0 |
0 |
1 |
ADC1 |
|
0 |
1 |
0 |
ADC2 |
|
0 |
1 |
1 |
ADC3 |
|
1 |
0 |
0 |
ADC4 |
|
1 |
0 |
1 |
ADC5 |
|
1 |
1 |
0 |
ADC6 |
|
1 |
1 |
1 |
ADC7 |
Ø REFS1:0 – Reference Selection Bits – These bits are used to choose the reference voltage. The following combinations are used.
Ø ADLAR – ADC Left Adjust Result – Make it ’1′ to Left Adjust the ADC Result. We will discuss about this a bit later.
Ø MUX4:0 – Analog Channel and Gain Selection Bits – There are 8 ADC channels (PA0…PA7).
ADMUX Initialization:
ADMUX = (1<<REFS0);
ADCSRA – ADC Control and Status Register A
|
ADPS2 |
ADPS1 |
ADPS0 |
DIVISION FACTOR |
|
0 |
0 |
0 |
2 |
|
0 |
0 |
1 |
2 |
|
0 |
1 |
0 |
4 |
|
0 |
1 |
1 |
8 |
|
1 |
0 |
0 |
16 |
|
1 |
0 |
1 |
32 |
|
1 |
1 |
0 |
64 |
|
1 |
1 |
1 |
128 |
Ø ADEN (ADC Enable) bit : Setting this bit enables the ADC. By clearing this bit to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress will terminate this conversion.
Ø ADSC (ADC Start Conversion) bit : In Free Running Mode, you must set this bit to start the first conversion. The following conversions will be started automatically. In Single Conversion Mode, you must set it to start each conversion. This bit will be cleared by hardware when a normal conversion is completed. Remember that the first conversion after the ADC is enabled is an extended conversion. An extended conversion will not clear this bit after completion.
Ø ADFR (ADC Free Running Select) bit : If you want to use the Free Running Mode, you must set this bit.
Ø ADIF (ADC Interrupt Flag) bit : This bit is set when an ADC conversion is completed. If the ADIE bit is set and global interrupts are enabled, the ADC Conversion Complete interrupt is executed. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical 1 (!) to the flag. This has a nasty side effect : if you modify some other bit of ADCSR using the SBI or the CBI instruction, ADIF will be cleared if it has become set before the operation.
Ø ADIE (ADC Interrupt Enable) bit : When the ADIE bit is set and global interrupts are enabled, the ADC interrupt is activated and the ADC interrupt routine is called when a conversion is completed. When cleared, the interrupt is disabled.
Ø ADPS (ADC Prescaler Select ) bits : These bits determine the division factor between the AVR clock frequency and the ADC clock frequency. The following table describe the setting of these bits :s
Assuming XTAL frequency of 16MHz and the frequency range of 50kHz-200kHz, we choose a prescaler of 128.
F_ADC = 16M/128 = 125kHz.
ADCSRA initialization
|
ADCSRA = (1<<ADEN)|(1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0); // prescaler = 128 |
ADCL and ADCH – ADC Data Registers
These registers hold the result of the last ADC conversion. ADCH holds the two most significant bits, and ADCL holds the remaining bits.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, it is essential that both registers are read and that ADCL is read before ADCH.
Here is a code snippet to make a conversion of ADC3. The result is placed in r16 and r17. The AVR is running at 4MHz:
SFIOR – Special Function I/O Register
In normal operation, we do not use this register. This register comes into play whenever ADATE (in ADCSRA) is set to ’1′. The register goes like this.
The bits highlighted in yellow will be discussed as they are related to ADATE. Other bits are reserved bits.
- ADC Auto Trigger Source – Whenever ADATE is set to ’1′, these bits determine the trigger source for ADC conversion. There are 8 possible trigger sources.
ADC Initialization
//The following code segment initializes the ADC.
void adc_init()
{
ADMUX = (1<<REFS0);// AREF
ADCSRA = (1<<ADEN)|(1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0);// ADC Enable and prescaler of 128
// 16000000/128 = 125000
}
//Reading ADC Value
//The following code segment reads the value of the ADC. Always refer to the register description above for every line of code.
unsigned int adc_conversion()
{
// select the single channel 0~7
//default channel ADC0
ADCSRA |= (1<<ADSC);// start convertion
while(ADCSRA & (1<<ADSC));// wait for conversion to complete
return (ADC); //return value stored in ADC
}
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